The present invention relates to a sense amplifier circuit for sensing/amplifying a small potential difference, which is useful as, e.g., a data line sense amplifier for a dynamic semiconductor memory device (DRAM).
A sense amplifier circuit for sensing a small potential difference between two electrodes or signal lines and outputting a signal corresponding to the relative potential magnitude of them is one of basic circuits used in various semiconductor devices. FIG. 22 shows an example of a bit line sense amplifier circuit used in a DRAM or the like. A CMOS transistor circuit having an inverter structure made up of an nMOS transistor QN1 and a pMOS transistor QP1, and a CMOS transistor circuit having an inverter structure made up of an nMOS transistor QN2 and a pMOS transistor QP2 are inverse-parallelly connected between input/output nodes Q and /Q, thereby constituting a latch (flip-flop) sense amplifier circuit. The common source between the nMOS transistors QN1 and QN2 is connected to a ground terminal VSS via an activation nMOS transistor QN3, whereas the common source between the PMOS transistors QP1 and QP2 is connected to a power supply terminal VCC via an activation pMOS transistor QP3.
FIG. 23 shows the operation waveform of this circuit. In an initial state, nodes SN and SP are kept at VCC/2, and the input nodes Q and /Q have a small potential difference. In this state, when one activation signal EN changes to "H", and the other activation signal EP changes to "L", the flip-flop made up of the nMOS transistors QN1 and QN2 and the flip flop made up of the pMOS transistors QP1 and QP2 are activated. Then, the potential difference between the input nodes Q and /Q is magnified and one of Q and /Q of which the initial potential is lower than that of the other becomes VSS when the other of Q and /Q of which the initial potential is higher becomes VCC.
The latch sense amplifier circuit senses and amplifies the potential difference between the input nodes Q and /Q until the higher potential node changes to VCC and the lower potential node to VSS. Thus, this sense amplifier circuit is employed in most of the DRAMs in which a change in potential of the bit line caused by charges in memory cells is read out, amplified, and rewritten. In a sense amplifier circuit of this type, the time required for an output to reach VCC or VSS is shorter, as the initial potential difference between input signals is larger.
A known example of a sense amplifier circuit used in a high-speed bus system is one having an arrangement shown in FIG. 24 that is disclosed in U.S. Pat. No. 5,355,391 filed by Mark A. Horowitz, et al. This sense amplifier circuit senses and amplifies an input potential difference at a high speed with a combination of a first amplifier for sensing a small potential difference and a second amplifier for outputting a large-amplitude output. The first amplifier is constituted by MOS transistors M1, M2, M3, . . . , M9 and transfer gates T1 and T2, and senses the potential difference between the input terminals Q and /Q. The nMOS transistors M1 and M2 serve as a current source. The potentials of the input terminals Q and /Q are input to a pair of differential nMOS transistors M3 and M4 via the CMOS transfer gates T1 and T2. The PMOS transistors M8 and M9 serve as a load.
The potential difference between the two output nodes of the first amplifier is amplified by the second latch amplifier comprised of MOS transistors M10, M11, . . . , M15. The second amplifier has the same arrangement as that shown in FIG. 22.
FIG. 25 shows the operation waveform of the sense amplifier circuit in FIG. 24. In a standby state, Clk and /Clk are fixed to "L" and "H", respectively. In this state, the potentials of the input terminals Q and /Q are transmitted to the gate electrodes of the nMOS transistors M3 and M4 in the first amplifier. The drains of the nMOS transistors M3 and M4 float because the nMOS transistors M5 and M6 are OFF, and the common source between the nMOS transistors M3 and M4 also floats because the nMOS transistor M1 is OFF. The pMOS transistors M8 and M9 are OFF, and an nMOS transistor M16 is OFF. The active second amplifier fixes one of the output terminals Out and /Out to VSS and the other to VCC.
When the state changes to Clk="H" and /Clk="L" the nMOS transistors M1, M5, and M6 and pMOS transistors M8 and M9 are turned on to activate the first amplifier. At the same time, the nMOS transistor M16 is turned on to equalize the potentials of the output terminals Out and /Out. In this case, if the pMOS transistors M8 and M9 are designed to have sufficiently high drive abilities, a small potential difference around VCC/2 that reflects the input potential difference in the first amplifier can be detected between the output nodes Out and /Out.
When the state changes again to Clk="L" and /Clk="H", the nMOS transistors M5 and M6 are turned off to activate the second amplifier again and amplify the potentials of the output nodes Out and /Out to VCC and VSS, and vice versa.
The operation principle of the second amplifier is the same as in FIG. 22. As the gain of the first amplifier is larger than unity, i.e., the output potential difference of the first amplifier is larger than the input potential difference, the amplifier circuit in FIG. 24 can determine its output at a higher speed than the amplifier circuit in FIG. 22.
In the amplifier circuit of FIG. 24, noise is hardly generated at the input nodes Q and /Q because the first amplifier is inactive in a standby state, and the drains of the transistors M3 and M4 are disconnected from the output nodes Out and /Out. When Clk="H", the first amplifier is activated and the potentials at the sources and drains of the nMOS transistors M3 and M4 vary. At this time, since the transfer gates T1 and T2 are OFF, no noise flows back into the input terminals Q and /Q. Accordingly, this amplifier circuit is suitably used for an arrangement in which a plurality of amplifiers are connected to the same input terminal node, e.g., for a bus line for connecting a plurality of semiconductor chips on board.
For the sense amplifier circuit to operate, the levels of the control clock signals must change twice, as described above. In addition, this sense amplifier circuit consumes a large power because a punch-through current flows from VCC to VSS for the operation of the first amplifier while Clk="H" and /Clk="L".
The current can be suppressed by adjusting a gate bias VBIAS to the transistor M2. But the high-speed operation is not achieved when the transistor M2 limits the current to too small amount, because a sufficient gain of the first amplifier is not obtained, resulting in the small initial inputs potentials of the second latch amplifier.
On the other hand, the total power consumption due to the punch-through current can be suppressed if the operation period of the first amplifier, while Clk="H" and /Clk="L", is shortened. But the pulse widths of the clock signals Clk and /Clk must be decreased to shorten this period. A representative time to determine the output potential in the sense amplifier circuit is about 1 nsec. Therefore, with a pulse width larger than 1 nsec, the power is wastefully consumed.
In general, it is difficult to build a circuit that can output a short pulse with high precision within an actual semiconductor circuit when a signal line driven by the pulse has a large parasitic capacitance and a high parasitic resistance. For example, a signal line with a resistance of 1 k.OMEGA. and a parasitic capacitance of 1 pF has a transfer delay time of 1 nsec, so this signal line cannot accurately transfer a pulse having a time width of 1 nsec or less. To normally control the circuit, a pulse longer than 1 nsec must be generated and this excessively consumes power.
As described above, in the conventional sense amplifier circuit shown in FIG. 24, since the control signal must change twice, the speed cannot be increased with a large-parasitic-capacitance, high-parasitic-resistance control signal line, and the power consumption is large because the punch-through current flows from the power supply VCC to VSS for a predetermined period.